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<xentrac>I fed the README file for https://github.com/kragen/calculusvaporis to Claude Opus 5 today and asked it to implement a bit-serial version of it in Verilog. I haven't validated that it works yet, but `nextpnr-ice40 --freq 150 --up5k --json cv_core.json --verbose` reports that the 12-bit CPU core itself should require about 102 4-LUT logic elements out of an iCE40UP5K and run at 150 MHz

<xentrac>24 of the logic cells are only used as D flip-flops

<xentrac>for context, the iCE40UP5K has 5280 logic elements, and Lattice's smallest FPGAs like iCELP384 have 384 logic elements, so this is a very small CPU indeed

<xentrac>it requires 14 clocks per instruction though

<xentrac>and its instructions are really very limited indeed; the only arithmetic is NAND and subtraction, so you have to synthesize addition out of multiple instructions

<xentrac>also the iCELP384 doesn't have any RAM

<xentrac>if each 4-LUT is equivalent to about 10 gates, as in the case of SeRV <https://github.com/olofk/serv>, that works out to about 1000 gates. That would be about 200 chips, but I think a pretty large fraction of that is actually shift registers, which are more compact

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2026-09-07.log