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2026-02-05.log
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<aleksih>Oh by the way, using the AArch64 backend requires setting InsaneArchitecture = TRUE in M2-Planet, unfortunately. It was much less work that way. <janneke>aleksih: there's a number of feature branches that we'll probably want to rebase, we should probably look which ordering makes the most sense <janneke>there's "wip-gcc4" with mes-libc patches but that needs a fresh rebase onto latest "wip" too <janneke>and then there's wip-bootstrap-x86_64, although that's mostly mescc work <nimaje>wait, what does InsaneArchitecture mean when AArch64 counts as one, but x86 doesn't? <aleksih>nimaje: InsaneArchitecture allows 32-bit instructions to be built up from pieces by XOR (e.g. "rd_a0 rs_a1 mv" on RISC-V, consisting of three pieces) <matrix_bridge><Andrius Štikonas> Building it from pieces actually is very nice and helpful. We only need to deal encode small number of opcodes that way. <aleksih>Yeah. It might be good for performance and memory usage to also implement some special immediate encodings in hex2, like there are for RISC-V. Right now the port just does a "ldr pc+8; b +8; .word xyz" trick to get immediates <aleksih>M2-Planet does the same load-then-branch-over trick on aarch64, which I replicated in the mescc backend. But hex2 has RISC-V specific special syntax for shifted immediates. <matrix_bridge><Andrius Štikonas> well, yeah, it would be nicer if aarch64 can be implemented in a similar way as risc-v but I haven't looked at aarch64 encodings to see if it's easily possible