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2024-03-17.log
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<oriansj>hmm, thinking deeper on RISC-V I am curious why they didn't use R31 instead of R0 and they could have dropped the PC instructions entirely. As it is possible to use loads into R31 as cache prefetch hints (as it would be writing to the zero register); which is zero for all ALU instructions but for load/store if R31 is used as a source register they could be PC relative. and for the case of storing the contents of R31 to RAM, it would <oriansj>eliminate the need for AUIPC and removes the need to do a jump/link to get the PC into a normal register. <oriansj>then it would only take a handful of transistors to encode that behavior. <oriansj>I believe DEC Alpha called it phantom loads and it was the cheapest way to implement prefetching of pages <oriansj>(as effectively it was a load but had the property of not actually loading into any registers) <oriansj>correction: the jump behavior to get the PC is an x86 quirk. For RISC-V PC can be obtained by setting the U-immediate field of auipc to 0. <oriansj>but honestly one only needs the PC for Returns and PC relative loads/stores. Relative jumps don't need to expose the PC.