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2023-09-21.log

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<oriansj>muurkha: very easy to do unfortunately
<oriansj>and the erase is not about the SRAM but the flash block written; probably because of residual charge in the cells if a full write or an erase is not done and the impact on the non-updated bits
<muurkha>oriansj: yeah, I don't know if it's about writing a bit to 0 repeatedly disturbing the nearby bits, or if writing a bit to 0 repeatedly physically damages that bit, or if writing a bit to 1 has some effect (erased bits are all 1, like Dr. Bronner's soap)
<muurkha>I feel like in the first two possible cases you could solve that problem by only writing the new zeroes
<notgull>Is hex0 implemented for RISC-V?
<matrix_bridge><Jeremiah Orians> Yes and so are all of the steps to M2-Planet and a mescc port is in progress
<matrix_bridge><Jeremiah Orians> Which with some work will get us to tcc and go
<matrix_bridge><Jeremiah Orians> ^go^gcc^
<notgull>Which repo?
<ekaitz>notgull: that part that is missing there is the one I'm trying to fix
<matrix_bridge><Jeremiah Orians> Well there is https://github.com/oriansj/stage0-posix-riscv32 and https://github.com/oriansj/stage0-posix-riscv64
<matrix_bridge>Depending on if you want 32 or 64 risc-v as they are not 100% compatible
<notgull>Is there an equivalent to builder-hex0 yet?
<stikonas_>notgull: no, there isn't yet\
<stikonas>notgull: and then again, there are various ways you can approach this problem
<stikonas>you could say use u-boot that is already installed (some kind of BIOS equivalent then) to load the sources into memory and then do something like builder-hex0 but replace I/O with calls to memory, etc... It will be a bit more work than builder-hex0 but doable
<stikonas>if you want to avoid u-boot, then it's much harder problem, you need device specific I/O drivers, do boot sequence, etc...
<stikonas>notgull: but probably the easiest thing to do, would be assume u-boot with UEFI API (which u-boot has) and then port stage0-uefi to riscv
<stikonas> https://git.stikonas.eu/andrius/stage0-uefi
<matrix_bridge><Jeremiah Orians> Or if you have a specific hardware target in mind we can help you port builder-hex0
<stikonas>and at this stage I think we can call mescc port of riscv working, just unreleased
<matrix_bridge><Andrius Štikonas> at some point Jeremiah Orians: we need to get you into the same room with janneke to coordinate releases of stage0 and mes
<stikonas>UEFI route is probably the easiest
<stikonas>and since it uses u-boot, it's mostly cross-target once you implement it
<stikonas>actually, my board (visionfive2) also seems to support tianocore https://forum.rvspace.org/t/unlocking-new-possibilities-starfive-visionfive-2-sbc-now-supports-tianocore-edk-ii-uefi/2779
<stikonas>haven't tried it yet...
<matrix_bridge><Jeremiah Orians> Well janneke has my phone number, so he can always just give me a call
<matrix_bridge><Jeremiah Orians> Heck a bunch of people here should have it
<stikonas>anyway, I think ekaitz and I might first try to fix our last issue that prevents bootstrapping tcc
<stikonas>and then we'll know for sure that mes 0.25 won't need any further changes
<matrix_bridge><Jeremiah Orians> I am also available via: matrix, xmpp and signal