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2023-09-20.log
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<oriansj>it appears the RAM is 4224bytes in size per plane and each plane is a different chip; which is what allows them to be operated upon in parallel. <oriansj>and the page has to be erased between partial updates; so you'll have to write the whole page on every go <oriansj>so you can't randomly set a byte in a page but you can partially populate the data in a page up to the number of bytes you want to write into them <oriansj>unless they are using the address pins to indicate the address inside of the page inside of an 85h period <oriansj>in which case one can't use a vanilla address bus and a controller with timing logic would be needed to get those 2-5cycles spot on. <muurkha>those are all standard attributes of Flash, except that some chips use a 2K sector size (plus ECC bits) rather than 4K <muurkha>sometimes you *can* write the same page more than once, getting the AND of all the times you wrote it, but it isn't reliable <muurkha>I don't think that package contains two separate chips; I think it's just one chip <oriansj>muurkha: I don't think the data registers are Flash but SRAM <oriansj>as they are updated on every read/write <oriansj>and they lose their state if power is lost <muurkha>oriansj: yes, the data registers are updated on every read/write. but you don't have to erase them between partial updates <muurkha>I should see if it's possible to write data to that SRAM and read it back ;) <muurkha>it's possible I misunderstood what you were saying though