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2023-09-05.log
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<[exa]>muurkha: btw it's cool they squeezed 4MHz out of that; the theoretical limit for the epprom is like 8Mhz there <[exa]>running on sram this could be wild <muurkha>how fast do discrete async srams go? <muurkha>(by "discrete" I mean a RAM chip as opposed to RAM integrated onto your FPGA or something. not RAM made out of discrete transistors or cores) <[exa]>absolutely no idea there but there's not much in the way that would cause it to be very slow <[exa]>as in, the latency might be O(wire length + mosfet switch delay) <muurkha>well, you can build a mux to be quite slow if you don't care how fast it is <muurkha>also inside the chip, if you have a tiny little latch driving a huge bitline, it can take a while <muurkha>and in DRAM, sense amplifiers can take a while to decide which way they're going; I don't know if there are similar components in SRAM <muurkha>the limiting issue is often actually EMI. with single-ended signals, people limit slew rates on pin drivers to reduce the amount of EMI they're coupling into the power planes <muurkha>and a lot of old chips have the Vcc and GND pins maximally far apart, and only one of each, which dramatically increases the area enclosed in the magnetic loop that produces and receives EMI <muurkha>not to mention that DIP packaging creates huge and totally unnecessary big loops; PLCC is a bit better, but WLCSP/BGA cuts that shit way the fuck down <muurkha>getting past about 33 MHz typically requires a lot of attention to this kind of stuff in your board layout, though differential signaling can reduce the problem a lot <muurkha>adding to the problem is that like 80% of EEs have no idea about half the stuff I'm talking about above, and 30 years ago it was more like 97%