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2023-06-04.log

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<oriansj>good morning
<Christoph[m]>Good morning! 😁
<oriansj>The more I learn about hardware design, the more I start to think most of the problems in the software world are self-inflicted.
<oriansj>most of the hardware sins can be expressed as the cost of dealing with legacy binaries and refusing to accept that once a problem is punted into software, it sticks around forever.
<oriansj>RISC-V is extra guilty about that last bit
<oriansj>oddly OpenRISC came earlier and is more free than RISC-V but less supported?
<[exa]>oriansj: I'm always unhappy about the "assume C calls and stacks" but riscv didn't get too much biased that way, right?
<[exa]>(except for the few possibly specialized registers)
<oriansj>[exa]: well C calls are just architecture calls but I'll grant C stacks miss a good idea. But RISC-V misses the entire premise of stacks with its link register set via the jal/jalr instructions and utter lack of push or pop instructions (or even store-decrement/load-increment addressing modes)
<oriansj>Forth got right, that you should have separate argument and return stacks