<oriansj>It is both big and little endian and the instruction encoding looks spot on for hex0 <oriansj>and SuperH appears to already be supported by GCC <stikonas>well, as long as early hex encoding is easier than risc-v it should be good <oriansj>and it looks like it has been in GCC since v3.2 <oriansj>the hex encoding looks literally hex aligned with only 8bit immediates and only 16bit instructions <oriansj>So we will have to do jump load PC relative to load values larger than 8bit but that is a non-issue at this point. <oriansj>and there is an ICE40 FPGA for it out too <oriansj>so it might be a winner from the bootstrapping perspective <stikonas>except for mes, tcc stages where x86 is still a winner <oriansj>stikonas: very true but hey, that just gives us another option to provide going forward. ***civodul` is now known as civodul
***civodul` is now known as civodul