<muurkha>Hagfish: we're definitely making progress but there's still a long way to go <Hagfish>yeah, i hope that once people see that the once-thought-impossible tasks of reproducible builds and bootstrappable builds are "solved" (at least in a narrow sense) that it will motivate a new wave of contributors to tackle this final frontier <tinybronca[m]><Irvise_> "Sorry, not silicon as the..." <- you just trolled me <tinybronca[m]>Isn't there some sneaky tricks you can do to your bitstream like padding somehow if you don't trust a proprietary FPGA? I think I saw mention of it once but did not read <tinybronca[m]>libre PCB schematics are nice but mostly useless if you don't trust the ICs on them <muurkha>tinybronca[m]: there's a constellation of poorly understood questions around that issue, and I think the answer is that nobody has a clue at this point <muurkha>you can definitely come up with theoretical malicious FPGA designs (which as far as we know nobody has built) that can be defeated by shuffling your gates and padding your bitstream <muurkha>given a simple theoretical countermeasure like that, you can come up with more sophisticated malicious FPGA designs that defeat them <muurkha>the generalized problem of computing on encrypted data has been a hot research topic in cryptography for 44 years, and dramatic advances have been made in the field, but there's still nothing approaching a general-purpose computing system that can run safely on backdoored hardware <muurkha>if anybody is actually deploying such attacks we don't know about them and so we don't know how sophisticated they are <muurkha>so at this point it's sort of an arms race in which the other side may not actually exist <tinybronca[m]><muurkha> "you can definitely come up..." <- Is there any public code or documentation describing how to construct an FPGA? I can find libre toolchains for very few models with very few documented bitstream formats, but I have not seen anything about how to construct them or code to this nature. <tinybronca[m]>For example there is HDL code for soft cores to RUN on FPGAs or make ASICs from <pabs3>there are designs on github for fpgas <muurkha>I don't think I've seen HDL for how to make a CPLD but HDL isn't really relevant; CPLDs and even FPGAs are very simple, regular structures that are repeated many times <muurkha>the challenge is making them small, fast, and reliable, not getting the logical design to work <muurkha>with respect to CPLDs you can find full gate-level schematics in any CPLD datasheet <muurkha>tinybronca[m]: because the stuff the HDL leaves out is the hard part <muurkha>things like how big each transistor needs to be <pabs3>sounds like clear is the one to look at <muurkha>eFabless is doing first-class work, they're very impressive <muurkha>tinybronca[m]: generally FPGA datasheets also include a sort of illustrative schematic of a logic block. a logic block is definitely not quite as simple as a logic gate but at a logical level it's pretty simple <muurkha>typically you have a lookup table or two (of 16 to 64 bits), a D flip-flop, and some multiplexers that control where the inputs to the lookup tables come from and whether the LUT output is routed through the flip-flop <muurkha>and some SRAM cells which control the muxes <muurkha>in addition to the ones that are in the LUT itself <muurkha>there are lots of tradeoffs in things like LUT size, how you do the routing, whether you have some special extra logic for speeding up carry chains, other special functional blocks like multipliers, exactly how the routing works, etc. <muurkha>I don't know anything about FPGAs, I'm just a muurkha <muurkha>I have my first FPGA board here, I just got it a few weeks ago <pabs3>tinybronca[m]: keep in mind that OpenFPGA is abandoned, the Clear one isn't though <muurkha>I still haven't done so much as blink an LED with it <muurkha>I bought a book 25 years ago, Kevin Skahill's "VHDL for Programmable Logic". It's a terrible book, don't buy it <muurkha>so I've been failing to learn about FPGAs for probably longer than some of the people in the channel have been alive <tinybronca[m]>In fact the first time I found HDL code online I did not understand it or how relevant it was <muurkha>I did have a bit more of an idea after I read the book, but it's very shoddy, full of obvious errors <muurkha>there's probably a good book out there about FPGAs but that isn't it <tinybronca[m]>muurkha: why write a book then if you aren't so good at it... 🤨 <muurkha>tinybronca[m]: if you know a lot about VHDL you can probably make more money by designing hardware than by writing a book about doing so <muurkha>Google Scholar suggests D. L. Perry's "VHDL: Programming by Example" as a better alternative book, but that probably won't tell you much about FPGAs either <tinybronca[m]><muurkha> "with respect to CPLDs you can..." <- I have not looked into CPLDs ever, do you have examples of such datasheets that are public? (I don't care if there is NDA haha can be "naughty") <muurkha>for that Google Scholar has three recommendations: Brown, Francis, Rose, and Vranesic's 01992 book; Trimberger's 02012 book; and Kuon, Tessier, and Rose's 02008 book <muurkha>I haven't read any of them but I bet the last two are probably pretty good and the first one is probably outdated <muurkha>AFAIK all CPLD datasheets are public <muurkha>I don't think there has ever been a CPLD whose datasheet was subject to NDAs <muurkha>this dissertation from the OpenFPGA guy might be better than any of those three books though <tinybronca[m]><muurkha> "for that Google Scholar has..." <- someone on Libera got viley angry at me for suggesting prefixing a "0" was valid notation in base 10 <tinybronca[m]>because I had the opinion this was suboptimal notifier for octal digits <oriansj>tinybronca[m]: people have the right to have their own personal preferences and very few people accept 0t as the octal prefix <tinybronca[m]><oriansj> "tinybronca: people have the..." <- Hmm Wikipedia does not even mention 0t, but it says multiple modern languages now use "0o" <oriansj>tinybronca[m]: hence why I waid very few people accept it. But yes 0o is valid if not consistent with heX <theruran>pabs3: thanks for the link to the OpenFPGA dissertation! <theruran>I am glad that "only commercial options exist, so let's make a FOSS one" is an acceptable academic research topic :P <pabs3>sorry, must have misremembered re phd vs masters. I feel like this is more of a phd topic though <theruran>I'm a PhD student and I still don't think I could explain the difference <theruran>a master thesis can be done in less than 2 years :) <theruran>a PhD in my department must be completed in 10 years <theruran>I think a PhD requires depth of scholarship, and dissertations can reach book size. that master thesis is surprisingly brief and mostly filled with figures <Irvise_>Efabless and Google are now supporting open silicon. They have opened a PDK (silicon transistor design) called SKY-130 (Skywater). It is a 130nm node. <Irvise_>They are funding open projects. You can find the list for the MPW 3 in te link above. I don't know the exact meaning of MPV, but it is basically a batch of funding. They are already preparing 4 and 5. <Irvise_>Look into the projects in the link I sent. All are open. At the bottom there is a brutally simple FPGA. All the designs are routed, synthesised and etched on open technologies. <Irvise_>theruran: I personally do not worry. Quite a few of those ICs are opened and analysed under a microscope to see the actual silicon. No nasty things are done to it :P <Irvise_>This Channel covers this topic in detail. Projects, deadlines, schedules, technologies, etc. I would recommend to look into it. <Irvise_>He also made a small open silicon mini conference, it is worth lookimg into <theruran>if they can verify it independently then well.. <Irvise_>theruran: (Re: PhDs) I Max-Planck a PhD is max max max 4 years paid. You can go longer, but without pay. <Irvise_>Mostly because their ICs do not work since the PDK is too green and the projects are too :P <Irvise_>But they also like de-etching their own silicon. <Irvise_>There are quite cool projects there. *Irvise_ gets ready for work. See ya'. ***Guest8848 is now known as roptat
<stikonas[m]>theruran: 10 years for PhD sounds way too much. Most places in Europe is about 4 years if you do it full time. <theruran>stikonas[m]: in my department of systems engineering, many students are working full-time, usually as engineers of some sort. we provide an online option for everything pretty much <stikonas[m]>I was in maths department, almost nobody was working outside ***furrymcg1e is now known as furrymcgee
<oriansj>theruran: the reason why Google did it that way was as a cheap way to find talent and good ideas to copy from. <oriansj>not to mention get a generation of engineers familiar with their toolstack <oriansj>tinybronca[m]: no I was responding to theruran's comment: "Irvise_: kinda sus!" <tinybronca[m]>oriansj: okay hard to tell with no reply feature haha, I find it funny they ban the AGPL license haha <oriansj>well AGPL is one of the few licenses that can hurt a big company like that <unmatched-paren>i suppose AGPL is even more damaging to their beautiful pile of £££ <oriansj>unmatched-paren: but ask yourself, who do they have to distribute the source code to. GPL it can be all internal; AGPL includes their competition. <tinybronca[m]>oriansj: I am not convinced the Affero clause is solid enough to refer to hardware designs <oriansj>tinybronca[m]: well, you'll have to ask Google's Legal department to understand their reasoning but my guess it is probably along the lines of they don't feel it is worth the risk to even consider. *tinybronca[m] doesn't want Google involved <oriansj>tinybronca[m]: that is fine, you never have to use anything google ever touches if you don't want to. You have that right as an individual <unmatched-paren>oriansj: that isn't really always true. some people have to use google "services" for one reason or another; for example, some may be forced to do so because of work or school <oriansj>personally, I'll work with anyone and as a rule I will never say a bad word in public about anyone, to otherwise is just not productive. You can trash talk tools and methods all you want because it helps people learn how to do things better. Don't make enemies with potential allies or those who might help <unmatched-paren>oriansj: that is a rule I can respect, though, even though I disagree :) <oriansj>unmatched-paren: true, those who are forced because of life situations; can't avoid it but if you are an adult, you are free to choose what you put up with and who you put up with. <unmatched-paren>that wikipedia article pabs3 linked to seems to need a bit of work :P <oriansj>well, that is the great thing about wikipedia... <tinybronca[m]>Why 10 years when copyright on other stuff is life of author + bajillion years <tinybronca[m]>unmatched-paren: Sorry I thought you were responding to my link <oriansj>tinybronca[m]: well assuming moore's law using 24months to double, 2^5 or a factor of 32x improvement. Should be sufficient to stop it from being competitive in the market place but perhaps useful in other areas <oriansj>also even RMS is for shorter copyright durations (despite the fact it would weaken the GPL) <muurkha>"MPW" means "multi-project wafer". conventional silicon fabrication involves making up a set of photolithography masks each the size of a whole wafer, which is normally 300 mm, thus containing several dozen to several tens of thousands of copies of your chip <muurkha>tinybronca[m]: that's hilarious about the octal fury <muurkha>the cost of making up a mask set is pretty large and has been since the 01970s <muurkha>in order to teach a class on VLSI design, Carver Mead and Lynn Conway set up a nonprofit called MOSIS, which was the first MPW setup <muurkha>MOSIS packed all the designs done by all the students onto a single wafer, making up a single mask set for the whole class, instead of one mask set per chip design ("project") <muurkha>this reduces the number of each chip you get, and requires that all the chips on the same wafer use the same sequence of process steps <muurkha>but it lowers the cost of fabricating some prototypes to a much more appealing level <muurkha>like, a few years back the minimum price for some 350nm prototypes was under €2000 <oriansj>well if you got 100 prototypes and 100 people put in €20, seems pretty affordable to me but if you only got back 4 prototypes at €500, then yeah it might be a niche <muurkha>I think typically you get between 20 and 100 prototypes, yeah <muurkha>usually the first run doesn't work though <muurkha>and then you have to figure out why and fix it <muurkha>and getting back your 20 prototypes in a more modern process might cost half a million dollars <oriansj>muurkha: we don't need modern lithography processes for bootstrapping *yet* <oriansj>heck 350nm lithography is good enough for us to have 64bit processors <muurkha>well, that vendor (one of the ones through CMP when I checked their price list in 02010) was charging €650 per square millimeter <muurkha>the minimum was three square millimeters, thus the €1950 minimum <oriansj>how many transistors per square millimeter? <muurkha>my estimate was that that was about 600,000 transistors, but my estimate is very unreliable because I've never actually done this <muurkha>I was guessing that a transitor might be 4λ×10λ <oriansj>muurkha: fair and I am estimating we need 30K-40K transistors per processor. <muurkha>600,000 transistors is comparable to a 68030, an Intel i960, an ARM700, or four AVRs <oriansj>muurkha: I'm thinking more RISC-II level of complexity <muurkha>yeah, I think you can definitely do more than Berkeley RISC II <muurkha>also, the clock speed should be higher because those historical 0.6 megatransistor chips were fabricated in a 1-micron process node <oriansj>integer only with MMU should be good enough to get use to a good place <muurkha>so Dennard scaling ought to get you a significant speed boost <muurkha>LibreSOC has submitted a prototype in 180nm to Imec's shuttle service <oriansj>muurkha: I can work with just 1Mhz but yeah <oriansj>I even have the cash to cover a couple batch runs, so if more people are interested in doing that work: I am game <oriansj>avoid the firmware issue entirely by going straight to making our own processors, sounds cool to me <muurkha>historically foundry NDAs have been a huge pain, and I think eFabless/Skywater are more important on that front even than on the cost reduction front