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2021-09-15.log
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<stikonas>fossy: maybe you want to rebase my guile branch while I'm busy with risc-v work? <stikonas>if not, I can do it at some point later... <stikonas>other than that I don't expect significant difficulties... <stikonas>a bit annoying though that we couldn't bootstrap autogen (which is what I intended to use guile for)... <stikonas>fossy: writing (I guess) first ever riscv C compiler in riscv assembly <stikonas>well, at the moment I'm just porting cc_amd64 to riscv <stikonas>there isn't that much difference between different arches <fossy>as a starting point i guess? <stikonas>then I can just adjust which text I emit into M1 file <stikonas>anyway, I've got tokenization working now and I think global variables are detected and emitted into labels <stikonas>still need to implement all other C features <stikonas>but riscv binaries are quite fast in qemu <stikonas>hex'es in other arches should probably be fixed too.. <stikonas>I tried running aarch64 bootstrap in qemu, and it took maybe 15 minutes <stikonas>and I think without ELF section header those cause mprotect syscalls in qemu <stikonas>moving variables to either stack or CPU registers (risc has plenty of them) seems to run significantly faster <stikonas>since everything is read and written byte by byte <stikonas>this workaround also let me significantly reduce size of hex0 <stikonas>it went from something like 48x bytes to 392 <xentrac>it inspired me to write dernocua/text/term-rewriting-micro-interpreter.md. I'm currently trying to debug it, but currently the interpreter is over a kilobyte <ekaitz>i'm probably late to the party but did you guys see this? <oriansj>ekaitz: yeah I posted about https://libre-soc.org/ earlier this year. I look forward to it and the release of its design files. As I like having more options for improving control over our own computing. <oriansj>when they add MMU support and become able to boot a Linux, it'll become much more useful.