IRC channel logs

2020-12-06.log

back to list of logs

<fossy>yt: a qemu x86
<fossy>but this is in M1
<fossy>once I finish the bootloader it will load a kernel in M2-planet
<yt>fossy: ooooh that's exciting!
<OriansJ>very nice indeed
<OriansJ>I guess I should extend this then: https://github.com/oriansj/stage0/blob/master/x86/stage1/stage1_disk_copier.s
<xentrac>fossy: congratulations!
<xentrac>that's very exciting!
<OriansJ>fossy: I would like to report that your kaem work fixed all of the problems that I previously had in mescc-tools-seed
<OriansJ>oh and thank you yt for keeping the M1 DEFINEs between hex0 and hex1 consistent (saved me from having to look them up again)
<OriansJ>AArch64 hex1 has been reviewed and merged.
<yt>OriansJ: no problem, and thanks for the review. catm is up next: https://github.com/oriansj/mescc-tools-seed/pull/14
<yt>I've cleaned up all the other tools and split them off, but I don't think GitHub handles dependent pull requests very well, so I'll post them as they are merged
<OriansJ>I'll hammer on catm tomorrow morning.
<fossy>OriansJ: that is very good news!! I am glad
***clever_ is now known as clever
<OriansJ>TIL baby gates can be broken faster than their boxes can by an agressive 9 month old with a block of wood and kicking.
<OriansJ>It was metal and rated for 6-36months
<OriansJ>yt: catm is merged; thank you
<OriansJ>hey civodul we are making great progress with AArch64 being bootstrapped this week ^_^
<civodul>hi OriansJ! yay!
<civodul>sounds like good news :-)
<bauen1>wow this is awesome
<civodul>i heard dannym had +/- a working port of Mes to ARMv7
<civodul>is that related?
<OriansJ>civodul: lower level; the mescc-tools-seed
<civodul>neat
<civodul>great news
<yt>OriansJ: great, thanks! I'll get hex2 up next
<yt>civodul: I've got half-way through a Mes port for AArch64, just need work's approval before I can put it up for review
<civodul>yt: oh nice!
<civodul>the ARMv7 backend should cover AArch64 in practice though, no?
<civodul>anyway, i'm glad we'll have all the arches that Guix supports covered :-)
<OriansJ>civodul: and hopefully help guix add even more ^_^
<yt>Arm processors won't support 32-bit forever; unlike x86_64, the 32-bit instruction set of Armv7 isn't a subset of the A64 ISA in Armv8
<yt>OriansJ: hex2 is up https://github.com/oriansj/mescc-tools-seed/pull/15
<OriansJ>yt: starting review
<OriansJ>civodul: think of Armv7 and Armv8 like RISC-II and RISC-V; nothing in common but the name. (And perhaps a handful of bad design decisions)
<janneke>yt: ah right -- i had the impression we'd be able to bootstrap aarch64 with arm
<yt>janneke: you probably can today, but you need a core that supports both A32 and A64 at (at least) EL0
<OriansJ>yt: or possibly EL1 if we wish for MesCC to be used to build a kernel https://hernan.de/blog/super-hexagon-a-journey-from-el0-to-s-el3/ ?
<yt>OriansJ: at EL1, A32 has already disappeared. Neoverse-N1 (the core in AWS graviton processors) already doesn't have it.