***terpri_ is now known as terpri
<OriansJ`>markjenkinsznc: if it makes life any easier for you "technically" HALT is just 0xFF, and NOP is 0x00; I just used 0xFFFFFFFF as HALT to make my disassembler's job easier and I made 0x00000000 as NOP; when I probably should have just defined that as NULL as it is what I ment. Although if I was being exactly true to the spec Knight doesn't support NOP operations and 0x00 was supposed to be an illegal instruction that should trap upon <plasma41>Where can I read more about the Knight TTL architecture? ***roptat_ is now known as roptat
<OriansJ`>plasma41: well I was going to implement knight in TTL and that is going to be what is going to be used. (I was planning on doing that after putting Knight on an FPGA via the iCEstorm toolset) It is on the backlog, after I get mes-m2 done. <plasma41>OriansJ`: In your talk-notes repository, the file 'bootstrabbable.org' describes knight as "a hardware specification that was implemented back in the 1970s in TTL". I have been unable to locate this specification. Where is it and could it be linked to from more places that mention knight? <OriansJ`>plasma41: fair, it is rather esoteric being a Computer designed by a failed company with only the marketing material surviving. However one must remember the architecture itself isn't important as I could just as easily write the pieces for a PDP-1 or even Magic-1 http://www.magic-1.org/ or a 6502 or z80. It was ultimately selected because it seemed like the architecture least likely to have an existing binary rootkit for. <OriansJ`>plasma41: good question, I'll have to find that in my notes' git history as it wasn't something I felt needed preservation; as it doesn't relate to the bootstrapping technical details that I thought mattered. <OriansJ`>It has been 5years since I last dealt with any of the original materials <plasma41>OriansJ`: My thinking is: If there's an existing specification for a TTL computer and if it can be used for bootstrapping, I want to know about it, so I can build one. <OriansJ`>plasma41: we already have existing machines readily available for bootstrapping implemented in TTL (PDP-10, VAX, etc) and more impressively Transistor-Diode logic (PDP-1) <OriansJ`>just such machines tend to cost $10K-100K to make <OriansJ`>and circuit diagrams are rare to say the least <OriansJ`>Not to mention the copyright issues associated with such diagrams <OriansJ`>Sometimes it is better to start with a clean white sheet and design according to a specification <OriansJ`>especially since we want truly libre-hardware <OriansJ`>Company name: Knight electronics and the machine's product name was Lilith. <OriansJ`>a 16bit processor with a rather sparse instruction set because the holes were going to be filled with 32, 64, 128 and 256bit instruction extensions <OriansJ`>which is what ultimately killed it in the market (wasteful of RAM) <OriansJ`>The knight 32bit follow up was supposed to be called Dawn <plasma41>OriansJ`: I can't find anything about Knight Electronics or the Lilith or Dawn computers in web searches. Where did you learn about them? <OriansJ`>plasma41: MSU engineering Library on one of my novelty first searches down a row <OriansJ`>literally only 16 of the 256 first byte values were used; <xentrac>oh, I had no iea that the Knight CPU came from a company; i thought it was your design <xentrac>I was looking at Wirth's RISC last night, which is probably feasible to implement in TTL (or more reasonably 74Cxx) <OriansJ`>xentrac: well modern CPUs are implemented in FPGAs <OriansJ`>(it is part of the current generation CPU design process); on FPGAs that cost $$$ <OriansJ`>now if the design was implemented on a $5 FPGA like the iCE40; then I would find that worth while <OriansJ`>as there are RISC-V designs on the 8K iCE40 <xentrac>Wirth's RISC has Oberon running on it <xentrac>it has 16 logic instructions, two memory instructions, branching instructions (from 1 to 64 of them depending on how you count), and a couple of interrupt-related instructions