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<OriansJ>xentrac: well PISC https://www.bradrodriguez.com/papers/piscedu2.htm only needs 22 TTL chips

<OriansJ>(Not counting the EPROM and RAM)

<xentrac>if you don't count EPROM, all you need is a register and RAM

<OriansJ>xentrac: only if you have a big enough EPROM

<OriansJ>but yes you are correct, EPROM and ROM are easy ways to "cheat" on chip counts when compared to individual gates

<markjenkinsznc>OriansJ, I just opened https://github.com/oriansj/stage0/issues/27 , I hope this isn't a distraction from other things like mes-m2, unless you're dying to fix it you can count on me solving it in a week or two

<markjenkinsznc>Proof of concept: https://github.com/oriansj/stage0/compare/master...markjenkins:M0nullpointerbug

<xentrac>oops

<xentrac>I don't think you need a very big EPROM

<xentrac> https://news.ycombinator.com/item?id=22362670 may be of interest; I tried to analyze how long different human artifacts would last

<OriansJ>markjenkinsznc: umm writing to address zero for knight isn't a null pointer dereference; however using store32 on a 16bit register set isn't a valid instruction

<OriansJ>now if one would replace the store32 with a store16; it would work on 16bit knight as well

<OriansJ>if anything the correct behavior is for knight16 to throw an invalid instruction exception on 32bit read/writes; just like it should be an invalid except for 64bit read/writes on 32bit versions. (or 256bit read/writes on 128bit machines)

<OriansJ>M0 on average requires double the amount of memory as the source file provided.

<OriansJ>I could get that down to 2KB + size of DEFINEs but it will slow things down a good bit.

<OriansJ>getting cc_x86 to run in 64KB however will require me to convert from a walk tokenization method to a pull tokenization method; a bit more complex but entirely possible

<markjenkinsznc>OriansJ, thanks. Have tried to follow up on GitHub but having issues there this morning. It makes total sense to me M0-macro.s shouldn't work on 16 bit mode because it has LOAD32 instructions, that is load 32 bits from memory to a register (must be at least 32 bits).

<markjenkinsznc>Semantically, STORE32 should be workable on 16bit as you can store a 16 bit value in 32 bits of memory, but no point if several calls to LOAD32 have already made trouble

<markjenkinsznc>I'm going to try and wrap my head around LOAD/STORE32 in a 64 bit context as I feel like that should be workable.

<markjenkinsznc>Could retitle my github issue or just close and re-open if I can articulate a good case for that (will discuss in chat before opening a new one)

<xentrac>so https://mysterymath.github.io/simple_cpu/ was a CPU built out of an SRAM chip, four EEPROMs, two pulllup resistors, and four LEDs with current-limiting resistors

<xentrac>but maybe that's a little unfair since those EEPROMs are serial EEPROMs, not regular parallel EPROMs like a 2764

IRC channel logs

2020-02-19.log